Inverter systems such as the one illustrated in FIG. 1A are known for driving AC motors, particularly as applied to controlling medium and high voltage AC motors. Such systems employ multiple inverter cells to convert multi-phase AC power to DC power, and then, to “invert” the DC power back to multiple waveforms of AC power. The inverter cell outputs are controlled using pulse-width-modulation techniques to determine the phase and amplitude of the waveforms in a prescribed manner.
Inverter system 100 in FIG. 1A, for example, employs three single-phase inverter cells, 103a, 103b, and 103c, configured to produce three voltage waveforms at nodes U, V, and W for driving the three-phase motor 104. Each cell outputs a waveform across the U0 to V0 terminals, with the V0 terminals connected together at a wye connection, and with each of the U0 terminals connected to one of the three phase output terminals U, V, and W, respectively (the choice of “U” “V” and “W” herein for the three-phase output, and the “U” and “V” inverter cell output terminals, is for convenience of notation). The wye connection creates a common reference point for all three outputs U, V, and W, and the inverter system is configured to generate the waveforms at 120° phase offsets from one another. At the inputs of the inverter system, inverter cells 103a, 103b, and 103c each have two 3-phase inputs 102a&b, 102c&d, and 102e&f, respectively, coupled through transformer 101 to a three-phase power source.
FIG. 1B is a vector representation of the output of the inverter system shown in FIG. 1A. Each vector of the figure represents the output waveforms between the common wye connection X and each of the inverter system output terminals U, V, W. The vectors point in 120° phase difference from one another, and each vector has a magnitude of “e.” When the outputs have phase offsets of 120°, the terminal-to-terminal outputs, eu-v, ev-w, and ew-u, each have a magnitude of:eu-v=e√{square root over (3)}=1.73e 
Inverter systems for medium and high voltage applications often make use of single-phase neutral-point-clamp (NPC) type inverter cells. FIG. 1C illustrates a typical NPC inverter cell circuit 103 used in the inverter system 100. Inputs 102a and 102b couple input power through transformer 101 to rectifier bridges REC1 and REC2 which convert the received AC power into DC power across smoothing capacitors C1 and C2 respectively. GTR1A&B, GTR2A&B, GTR3A&B, and GTR4A&B are switch pairs, of any type of switching device, controlled with a pulse-width-modulation (PWM) control system (not shown) to invert the DC power to AC power across output terminals U0 and V0. Diodes D1, D2, D3, and D4 are clamp diodes connected between the center of each switch pair and the “neutral” point C of the inverter cell.
FIG. 2A illustrates another known multi-cell inverter system for obtaining higher output voltages than can be achieved by the inverter system illustrated in FIG. 1. The inverter system in FIG. 2A utilizes six inverter cells. Inverter cells 103a, 103b, and 103c of FIG. 2 are identical to the inverter cells in FIG. 1. Additional inverter cells 103d, 103e, and 103f have outputs connected in series with the outputs of 103a, 103b, and 103c respectively to boost the voltage on the three outputs U, V, and W of the system. As shown in the vector diagram in FIG. 2B, the additional cells produce outputs of the same magnitude and phase as the cells to which they are serially connected causing the serial combination of cells to produce twice the voltage of a single inverter cell at each phase output of the inverter system. The terminal-to-terminal output voltages, eu-v, ev-w, and ew-u are equivalent, and are as follows:eu-v=2e√{square root over (3)}=3.46e                 (e being the output voltage of a single cell)        
The inverter system of FIG. 2A can support higher voltage levels, but it uses twice as many inverter cells as the FIG. 1 system. If the FIG. 2A configuration were used to support the same voltage levels as the FIG. 1 system, then the FIG. 2A system could be implemented with lower-rated (and lower cost) inverter cells, but the additional cells still increase the risk of failure because there are more devices that could fail.
FIG. 2C illustrates another configuration, in which three of the single-phase cells from the FIG. 2A configuration are replaced with a single three-phase inverter cell TP1, and used with three NPC single-phase cells. FIG. 2D illustrates the vector configuration for FIG. 2C, and as illustrated, the FIG. 2C configuration can also be used to support higher voltage levels than the FIG. 1 configuration, but the FIG. 2C configuration requires two different types of inverter cells (three-phase and single-phase). Accordingly, there remains a need to support higher voltage levels, while also minimizing the risk of failure (and cost).